Entry-Level Physical Design & Verification Engineer
Focused on RTL-to-GDSII flow, functional verification, timing analysis, and DFT-aware digital design.
Focused on RTL-to-GDSII flow, functional verification, timing analysis, and DFT-aware digital design.
I am a graduate Electrical & Computer Engineering student with a strong interest in Physical Design and Digital Verification for semiconductor systems.
My experience includes RTL design in Verilog/SystemVerilog, functional verification, synthesis, timing analysis, scan-based DFT concepts, and PPA evaluation using industry-standard EDA tools.
I am actively seeking entry-level opportunities in Physical Design or Verification Engineering.
M.S. Electrical & Computer Engineering — GPA: 3.0 / 4.0
B.Tech Electronics & Communication Engineering — GPA: 3.5 / 4.0
Problem: Ensure functional correctness and manufacturability.
Approach: RTL design, scan insertion, ATPG using Synopsys tools.
Outcome: 98.72% fault coverage with PPA analysis.
Problem: Reduce leakage in sub-45nm CMOS.
Approach: SVL-based design with parity fault detection.
Outcome: Reduced leakage and validated timing.
Outcome: 18% reduction in total travel distance.
Synopsys • Associate Level
Email: devaramsucharith@mail.fresnostate.edu
LinkedIn: linkedin.com/in/sucharithsdevaram